`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:23:01 04/20/2011 
// Design Name: 
// Module Name:    Mux_2to1_16bits 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Mux_2to1_16bits(a, b, sel, out);
    input [15:0] a;
    input [15:0] b;
    input sel;
    output [15:0] out;

	reg [15:0] out;
	
	always @ (*)
	begin
		if (sel == 0)
			out <= a;
		else
			out <= b;
	end
	
endmodule
